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Co-planar two-dimensional Metal-Insulator-Semiconductor Capacitor: Numerical study of the device electrostatics.

preprint
submitted on 12.09.2017 and posted on 15.09.2017 by Varun Bheemireddy
The two-dimensional(2D) materials are highly promising candidates to realise elegant and ecient transistor. In the present letter, we conjecture a novel co-planar metal-insulator-semiconductor(MIS) device(capacitor) completely based on lateral 2D materials architecture and perform numerical study of the capacitor with a particular emphasis on its di erences with the conventional 3D MIS electrostatics. The space-charge density features a long charge-tail extending into the bulk of the semiconductor as opposed to the rapid decay in 3D capacitor. Equivalently, total space-charge and semiconductor capacitance densities are atleast an order of magnitude more in 2D semiconductor. In contrast to the bulk capacitor, expansion of maximum depletion width in 2D semiconductor is observed with increasing doping concentration due to lower electrostatic screening. The heuristic approach of performance analysis(2D vs 3D) for digital-logic transistor suggest higher ON-OFF current ratio in the long-channel limit even without third dimension and considerable room to maximise the performance of short-channel transistor. The present results could potentially trigger the exploration of new family of co-planar at transistors that could play a signi significant role in the future low-power and/or high performance electronics.

History

Topic

  • Nanodevices
  • Nanostructured Materials

Email Address of Submitting Author

b.varun163@gmail.com

Institution

IISER Kolkata

Country

India

ORCID For Submitting Author

0000-0002-5267-124X

Declaration of Conflict of Interest

no conflict of interest

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